Stuck-at fault models are conventionally used to detect faults that behave as if a gate or wire is tied to power or ground. Transition fault models are used to detect faults that cause extra delays in circuitry. Two clock pulses are used to detect a transition fault within each clock domain. An initial pulse launches the transition that activates the fault and a subsequent pulse captures the fault effect of the transition.
If a frequency of the clock is low (typically less than 200 megahertz (MHz)), the launch pulses and the capture pulses are supplied from chip pins. Due to limitations of tester electronics and speeds of the chip pins, generation of the launch pulses and the capture pulses is commonly performed on-chip if the clock frequency is greater than 200 MHz. Most conventional clock control circuits are limited to generating pulses for a single clock domain. However, the pulses generated on-chip by several clock control circuits in several clock domains are often asynchronous with each other making the inter-clock domain transition testing difficult.
It would be desirable to implement synchronized clocks to detect inter-clock domain transition defects.